1. Field of the Invention
The present invention relates to dual port memory systems and, in particular, to collision detection in dual port memory systems.
2. Discussion of Related Art
In many computational systems, the ability for two or more processors to access the same memory array, and in particular the same memory location, simultaneously has become important. For example, the ability for peripheral devices and a processor in a computer system to access the same memory array allows for transfer of data to the peripheral devices, or even between peripheral devices, without intervention of the processor itself. In some systems, such a memory system allows multiple devices operating according to different clock signals to pass information between the devices without synchronizing the clocks. Additionally, fast switching of data in communications systems can be attained when different devices can simultaneously access the same memory locations.
Multi-port memory systems allow multiple devices to utilize the same memory array at the same time. In general, each of the devices can read and write to the memory array. The memory array can utilize multi-port memory cells to allow simultaneous access to any address in the memory array from any of the ports. In some embodiments, a pipelining circuit at each port can control data and address inputs and can provide minimal setup and hold times. In general, a wide variety of options and features (e.g., pipelining or flow-through modes, synchronous operations on one or multiple ports, separate byte controls for read and write operations, packaging features, and support for various standards) can be available on a multi-port memory system.
Dual port memory systems, for example, can be utilized in mobile and wireless technologies, networking applications, storage area networks, enterprise systems, and other systems. Dual port memory systems are particularly useful in high speed routers, switches, and other networking environments. Further, dual port memory systems are useful in graphics and multi-media applications, medical applications, and signal processing.
With two or more independent processors potentially capable of accessing the same memory location in the memory array at the same time, the potential for both processors to attempt access to the same memory location at the same time is high. In some cases, the attempts by both processors to access the same location can result in the erroneous readout of data or the erroneous write of data to the memory array.
Schemes have been devised to prevent such dual access of the same memory location within the memory array. In some approaches, the ports are arbitrated such that the first port that requests access to the memory location has priority and a second port attempting access to the same memory location receives a busy signal until the first port has completed its operation at which time the second port can gain access to the memory location. Such an arbitration scheme is described in European Patent Application 86101935.4, EP 0192209 A1, filed by Honeywell, Inc., on Feb. 15, 1986. In another approach, such as that described in U.S. Pat. No. 5,398,211 issued to Willenz et al. on Mar. 14, 1995, one port always has priority over all other ports. Other ports that attempt to access a particular memory location will obtain a busy signal during this time the preferred port requests access to that memory location.
However, schemes for arbitrating access to memory locations within a memory array when contentions occur can significantly decrease the throughput of a memory device. In certain sequential systems, bandwidth can be high, especially in telecommunications systems where fast switching of digital data between devices can be required. Contention methods that slow the data flow rate, such as arbitration scheme circuitry, are not desirable.
Therefore, there is a need for multi-port memory systems with the capability to recognize and handle simultaneous accesses by each port a single memory location in a memory array without affecting the bandwidth of the multi-port memory system.